High-speed data communication systems frequently rely on clock and data recovery (CDR) circuits within the receiver rather than transmitting a reference clock with the data. For example, serial data communication may include the use of a serializer-deserializer (SERDES) at each end of a communication link. Within a SERDES, a CDR may extract a clock that is embedded in the incoming data stream. Once a clock is recovered, the clock is used to sample the incoming data stream to recover individual bits.
A bang-bang CDR scheme is widely used in digital logic to identify the best dock phase to capture the received data. In a bang-bang CDR scheme, the received signal is oversampled to obtain data samples and crossing samples (also referred to as edge samples). A bang-bang CDR uses the data samples and the crossing samples to determine if the data sampling phase should be adjusted, in which direction the data sampling phase should be adjusted, and where to stop the adjustment. Once the data sampling phase dithers around the “best” sampling position, the bang-bang CDR is locked.
There is a scenario where the data sampling phase falls at the crossing area when the system starts, which results in a longer time to lock. This condition is referred to as meta-stability. In the meta-stable condition, the phase detector in the CDR may not effectively generate decisive signals to push the CDR to lock quickly. Eventually, the CDR can exit the meta-stable state and lock to the correct phase due to external interference, but the lock times can be long. It is desirable to minimize lock times and avoid meta-stable conditions in a CDR circuit.